Counters are used in many computer applications. One example is keeping track of data flow into and out of a data buffer. As an example application, a buffer such as an asynchronous FIFO (First In First Out) buffer can be used to transfer data between two processors that have different clock speeds, for instance, between the main processor of a personal digital assistant (PDA) and a wireless communication processor in the PDA that is used to communicate with, e.g., the Internet. A FIFO essentially removes protocol overhead and data delivery time issues that are present in such applications. FIFO=s are especially useful in EMI sensitive systems such as, for example, a PDA that has a communication processor which is sensitive to electrical noise.
Counters are necessary in such applications so that it can be determined if the buffer is full, partially full compared to a threshold, partially empty compared to another threshold, and completely empty. These determinations can be used to properly establish various communication and data processing parameters.
A common counter is the binary counter, which simply counts, using binary math, how many bits it “sees” going into or out of an associated buffer. As recognized by the present invention, however, in an application requiring low electrical noise, such as the above-mentioned communication processor application, binary counters suffer from the drawback that in certain transitions between counts, a relatively large amount of electrical noise can be generated. For instance, when a binary counter is reset from its maximum value to zero, all the bit values in the counter transition simultaneously from one to zero, generating a relatively large amount of electrical noise.
Gray code counters, in contrast, are counters that never have more than one bit change in a single clock cycle. That is, a Gray code counter can be desired because only one bit of the count is allowed to change on each clock edge, whereas as mentioned above with a binary count the number of bits that change is from one up to the width of the counter. Furthermore, Gray coded counters also offer the best metastable characteristics in asynchronous FIFO designs due to the minimal spread of bit transitions across time, thereby minimizing or completely eliminating unwanted spurious comparator outputs and attendant spurious FIFO flag generation and resetting.
The present invention further understands, however, that implementing a Gray code counter in logic is not as trivial as implementing a simple binary counter. Indeed, the logic resources required to do so, and the performance subsequently achieved, can vary considerably between compilers. Specifically, while optimization of a Gray code counter can be achieved when the reset value of the counter is known, problems arise when the counter is made generic in width and has a reset value that is undetermined at compile time.
One method of guaranteeing that the implementation functions correctly is to use explicit lines of logic code that define the state of the counter after each clock edge, but this method is at the mercy of the compiler=s optimizer to ensure the most efficient use of logic. In addition, it is extremely difficult to write generic code for a scalable counter that uses such explicit instructions. Nevertheless, such a generic Gray code counter is desirable because in many applications the reset value can and does change, depending, for instance, on changing universal asynchronous receiver/transmitter (UART) speed during operation.